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Silicon Labs /EFR32MG21B010F512IM32 /PRS_NS /ASYNC_CH5_CTRL

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Interpret as ASYNC_CH5_CTRL

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https://regviz.com/r/Silicon Labs/BGM210LA22JNF/PRS_NS/ASYNC_CH5_CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NONE)SIGSEL 0SOURCESEL0 (LOGICAL_ZERO)FNSEL

FNSEL=LOGICAL_ZERO, SIGSEL=NONE

Description

No Description

Fields

SIGSEL

Signal Select

0 (NONE): undefined
SOURCESEL

Source Select
FNSEL

Function Select

0 (LOGICAL_ZERO): Logical 0

1 (A_NOR_B): A NOR B

2 (NOT_A_AND_B): (!A) AND B

3 (NOT_A): !A

4 (A_AND_NOT_B): A AND (!B)

5 (NOT_B): !B

6 (A_XOR_B): A XOR B

7 (A_NAND_B): A NAND B

8 (A_AND_B): A AND B

9 (A_XNOR_B): A XNOR B

10 (B): B

11 (NOT_A_OR_B): (!A) OR B

12 (A): A

13 (A_OR_NOT_B): A OR (!B)

14 (A_OR_B): A OR B

15 (LOGICAL_ONE): Logical 1

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data